This thesis is mainly concerned with discrete time sigma-delta modulators aimed for the digitisation of narrow- and wide- band signals present in multi standard wireless receivers. For this purpose, a receiver architecture is proposed, where the analogue to digital conversion of narrow band signals is carried out at low values of intermediate frequency, while wide-band signals are being converted at zero-IF. In order to preserve the low power consumption requirements demanded by mobile terminals, an A/D converter able to reach high values of signal-to-noise ratio by using modest oversampling ratios is needed. Another characteristic, that should be exhibited by the converter is flexibility, since it has to work in a multi mode environment handling with different intermediate frequencies, channel bandwidths and modulation techniques. Single Bit High Order sigma-delta Loops appear to be good candidates to full fill the mentioned needs. They are able to achieve high values of SNR for low OSR's and their circuit implementation is very robust. They also have the interesting characteristic of synthesizing different types of noise transfer functions by changing the filter loop coefficients without altering the structure of the modulator. In order to improve both resolution and stability of single bit high order SDM's, quantization noise suppression should be carried out not only at DC but also within the band of interest. This noise suppression at frequencies different form zero is carried out with the use of resonators. Switched Capacitor resonators at base band can be designed using integrating or delaying elements. In this work, both resonator structures were analysed with respect to their robustness against the main imperfections presented in a SC implementation. The effect introduced by the operational transconductance amplifiers (OTAs) nonidealities was analysed together with the effect of capacitor mismatch. The conducted study shows the superior performance of the integrator based resonator over delay based structures. The robustness exhibited by this resonator at frequencies within baseband makes it a good candidate for the implementation of wide band ADCs. Using the integrator based resonator and the ability of single bit loops to synthesize different NTFs by changing the coefficient set, a prototype of a 4th order multi-mode SD modulator was designed. Care was put in this design in producing a flexible prototype, which could be used for the conversion of both narrow and wide band signals. This experimental prototype was fabricated in a 0.35 micro meters CMOS technology using a core area of 0.19sqmm. It consumes 48.6mW from a single 3.3V power supply and achieves a peak SNR of 72dB over a bandwidth of 200 kHz when clocked at 16 MHz. For wideband signals the measurements showed a resolution of 53dB if the bandwidth extends to 1.92 MHz, as required by UMTS signals. In this case the prototype was clocked at 76.8 MHz, which produces an OSR of 20.