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An Efficient Hardware Design for a Low-Latency Traffic Flow Prediction System Using an Online Neural Network

Hanafy, Yasmin Adel ; Mashaly, Maggie ; Abd El Ghany, Mohamed A. (2024)
An Efficient Hardware Design for a Low-Latency Traffic Flow Prediction System Using an Online Neural Network.
In: Electronics, 2021, 10 (16)
doi: 10.26083/tuprints-00019595
Article, Secondary publication, Publisher's Version

Copyright Information: CC BY 4.0 International - Creative Commons, Attribution.

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Item Type: Article
Type of entry: Secondary publication
Title: An Efficient Hardware Design for a Low-Latency Traffic Flow Prediction System Using an Online Neural Network
Language: English
Date: 12 January 2024
Place of Publication: Darmstadt
Year of primary publication: 2021
Place of primary publication: Basel
Publisher: MDPI
Journal or Publication Title: Electronics
Volume of the journal: 10
Issue Number: 16
Collation: 22 Seiten
DOI: 10.26083/tuprints-00019595
Corresponding Links:
Origin: Secondary publication DeepGreen

Neural networks are computing systems inspired by the biological neural networks in human brains. They are trained in a batch learning mode; hence, the whole training data should be ready before the training task. However, this is not applicable for many real-time applications where data arrive sequentially such as online topic-detection in social communities, traffic flow prediction, etc. In this paper, an efficient hardware implementation of a low-latency online neural network system is proposed for a traffic flow prediction application. The proposed model is implemented with different Machine Learning (ML) algorithms to predict the traffic flow with high accuracy where the Hedge Backpropagation (HBP) model achieves the least mean absolute error (MAE) of 0.001. The proposed system is implemented using floating point and fixed point arithmetics on Field Programmable Gate Array (FPGA) part of the ZedBoard. The implementation is provided using BRAM architecture and distributed memory in FPGA in order to achieve the best trade-off between latency, the consumption of area, and power. Using the fixed point approach, the prediction times using the distributed memory and BRAM architectures are 150 ns and 420 ns, respectively. The area delay product (ADP) of the proposed system is reduced by 17 × compared with the hardware implementation of the latest proposed system in the literature. The execution time of the proposed hardware system is improved by 200 × compared with the software implemented on a dual core Intel i7-7500U CPU at 2.9 GHz. Consequently, the proposed hardware model is faster than the software model and more suitable for time-critical online machine learning models.

Uncontrolled Keywords: direct memory access, field programmable gate array, Hedge Back Propagation, online neural network
Status: Publisher's Version
URN: urn:nbn:de:tuda-tuprints-195959
Additional Information:

This article belongs to the Section Artificial Intelligence Circuits and Systems (AICAS)

Classification DDC: 600 Technology, medicine, applied sciences > 621.3 Electrical engineering, electronics
Divisions: 18 Department of Electrical Engineering and Information Technology > Institute of Computer Engineering > Integrated Electronic Systems (IES)
Date Deposited: 12 Jan 2024 14:51
Last Modified: 12 Mar 2024 14:48
SWORD Depositor: Deep Green
URI: https://tuprints.ulb.tu-darmstadt.de/id/eprint/19595
PPN: 516174312
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