Information is an increasingly important factor in today’s world. In particular, the acquisition of physical parameters and their processing are essential for modern applications. Every technical device provides users with ever more precise information about the environment. However, the demand for even more detailed information grows steadily. An Analog-to-Digital Converter (ADC) translates the physical signals into computer-processable representations to provide this information to the consumer’s application. Representing a more detailed version of the environmental information is now limited by the technical realization of this crucial component. As a result, researchers need to establish new ways to meet the demand for growing information. Today’s ADCs usually quantize the information in a one-dimensional way within an equidistant sampling. How- ever, this approach neglects physical signals in two dimensions - in magnitude variations and time variations. While ADCs realize the magnitude quantization with high accuracy, the representation for the resolution in time is usually insufficient. However, a detailed conversion of both dimensions implies a higher information density. Non-uniformly sampled signals represent an alternative, as these retain the relationship to a dynamic variation in the physical signal. As a solution, a completely new method for a high information density conversion based on non-uniform sampling presents the Algorithmic Tracking Scheme ADC. The conceptual basis proposes an ADC that compares the physical input signal to a dynamic reference generated by algorithmic implementations. This proposal leads to fundamental research questions: What is the significance of the reference signal? Which constitution of the reference signal influences the information density? How to realize technical approaches? The analysis of the information density answers these questions. In this context, a mathematical description derives the fundamentals for the study of information density. Possible sampling algorithms are derived from these equations and initialize a dynamic implementation of the ADC topology. As part of the concept evaluation, an FPGA configuration with analog element functionality implements the algorithms. Additionally, the ADC process was transferred and validated on three ASIC prototypes using state-of-the-art technologies and high-performance-computing technologies (65 nm, 65 nm, 28 nm). Both the derived equations and the measurement results mutually confirm each other. Thus, the proposed mathematical equations and design methodology provide a functional development tool for ADC designers.