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A Novel Design Flow for a Security-Driven Synthesis of Side-Channel Hardened Cryptographic Modules

Huss, Sorin ; Stein, Oliver (2024)
A Novel Design Flow for a Security-Driven Synthesis of Side-Channel Hardened Cryptographic Modules.
In: Journal of Low Power Electronics and Applications, 2017, 7 (1)
doi: 10.26083/tuprints-00016594
Article, Secondary publication, Publisher's Version

Copyright Information: CC BY 4.0 International - Creative Commons, Attribution.

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Item Type: Article
Type of entry: Secondary publication
Title: A Novel Design Flow for a Security-Driven Synthesis of Side-Channel Hardened Cryptographic Modules
Language: English
Date: 16 January 2024
Place of Publication: Darmstadt
Year of primary publication: 2017
Place of primary publication: Basel
Publisher: MDPI
Journal or Publication Title: Journal of Low Power Electronics and Applications
Volume of the journal: 7
Issue Number: 1
Collation: 20 Seiten
DOI: 10.26083/tuprints-00016594
Corresponding Links:
Origin: Secondary publication DeepGreen

Over the last few decades, computer-aided engineering (CAE) tools have been developed and improved in order to ensure a short time-to-market in the chip design business. Up to now, these design tools do not yet support an integrated design strategy for the development of side-channel-resistant hardware implementations. In order to close this gap, a novel framework named AMASIVE (Adaptable Modular Autonomous SIde-Channel Vulnerability Evaluator) was developed. It supports the designer in implementing devices hardened against power attacks by exploiting novel security-driven synthesis methods. The article at hand can be seen as the second of the two contributions that address the AMASIVE framework. While the first one describes how the framework automatically detects vulnerabilities against power attacks, the second one explains how a design can be hardened in an automatic way by means of appropriate countermeasures, which are tailored to the identified weaknesses. In addition to the theoretical introduction of the fundamental concepts, we demonstrate an application to the hardening of a complete hardware implementation of the block cipher PRESENT.

Uncontrolled Keywords: side-channel analysis, secure CAE design
Status: Publisher's Version
URN: urn:nbn:de:tuda-tuprints-165946
Additional Information:

This article belongs to the Special Issue Hardware Security – Threats and Countermeasures at the Circuit and Logic Levels

Classification DDC: 600 Technology, medicine, applied sciences > 621.3 Electrical engineering, electronics
Divisions: 18 Department of Electrical Engineering and Information Technology > Integrierte Schaltungen und Systeme
Profile Areas > Cybersecurity (CYSEC)
Date Deposited: 16 Jan 2024 10:38
Last Modified: 02 Apr 2024 11:10
SWORD Depositor: Deep Green
URI: https://tuprints.ulb.tu-darmstadt.de/id/eprint/16594
PPN: 516705245
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