Communication Infrastructure Modeling of Many-Core Architectures

Many-core architectures are becoming a standard design alternative for embedded systems. The force that is driving to this direction is the contradiction that improving the battery lifetime of a chip requires a reduction of the power consumption, but improving the performance of a chip by increasing the clock frequency increases the power consumption. As there is no solution for this problem, the alternative is to introduce several cores to a chip and make them work in parallel. However, going from single-core to many-core architectures is not straightforward and this is the main concern of this thesis. It requires both new programming methodologies for using multiple cores in parallel and an efficient communication infrastructure to interconnect these cores. A monitoring system connected to the communication infrastructure is also recommended to provide feedback to dynamic task mapping and task migration algorithms. This thesis contemplates the following issues related to many-core architectures: creation of a many-core architecture model with emphasis on the communication infrastructure, modeling of applications over the many-core architecture model, support for a heterogeneous many-core architecture model, implementation of task mapping and migration algorithms, implementation of monitoring systems, and two different designs of a dual-layer Network-on-Chip that provides Quality-of-Service.