The Gigahertz clock rates in today's VLSI systems are not only due to advances in technology but thanks to aggressive use of pipelining as well. Pipelining is routinely used in computer arithmetic circuits like floating point multipliers to increase the clock frequency beyond that possible by latency reduction due to advanced circuits and technology. However, in fine grain pipelines where only a few gates constitute a stage the overhead in power, latency, and area caused by clock and latch infrastructure is dramatic. Wave pipelining is a technique to achieve pipelining while adding little latency penalty and latch overhead. In this thesis it is argued that wave pipelining can only possibly work asynchronously using self-resetting dynamic circuits. The dual-rail circuit family AWPCMOS making possible cycle times as low as six inverter delays is proposed for asynchronous wave pipelines and analyzed. As the wave pipeline throughput is ultimately limited by delay variation due to PVT and data dependency, emphasis is put on detailled analysis of sources of delay variation in AWPCMOS circuits. The concepts are evaluated by design, fabrication, and test of two chips, a pipelined 64-bit carry-lookahead adder and a pipelined 270-bit Massey-Omura optimal normal basis finite field multiplier for use in elliptic curve cryptography.