Optimal Design of Fixed-Point and Floating-Point Arithmetic Units for Scientific Applications.
TU Darmstadt, Darmstadt, Germany
[Ph.D. Thesis], (2012)
Available under Simple publication rights for ULB.
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|Item Type:||Ph.D. Thesis|
|Title:||Optimal Design of Fixed-Point and Floating-Point Arithmetic Units for Scientific Applications|
The challenge in designing a floating-point arithmetic co-processor/processor for scientific and engineering applications is to improve the performance, efficiency, and computational accuracy of the arithmetic unit. The arithmetic unit should efficiently support several mathematical functions corresponding to scientific and engineering computation demands. Moreover, the computations should be performed as fast as possible with a high degree of accuracy. Thus, this thesis proposes algorithm, design, architecture, and analysis of floating-point arithmetic units particularly for scientific and engineering applications which can be implemented in VLSI.
Generally, performance improvements and time efficiency with hardware can be considered from the output rate and the computational latency which is the number of generated outputs per second (output/sec) and the computational times. The output rate can be increased by clock rate whereas the design and architecture of the hardware can improve the computational time, which is mostly focused on engineering practice. Obviously, in order to achieve the highest performance, the design will be based on pipeline architecture. Nevertheless, for any hardware arithmetic unit, not only the performance and time efficiency have to be examined, but also the computational accuracy and stability of the computational results have to be taken into account. Therefore, the floatingpoint arithmetic units introduced in this dissertation will be considered in their design and architecture based on pipeline, and an analysis of the hardware trade-off between the VLSI areas of complexity and computational latency. Meanwhile, the floating-point data representation is employed to improve and stabilize the computational result and accuracy of the arithmetic unit at runtime.
The arithmetic units from a hardware point of view can be classified into two groups depending on hardware-based algorithms, i.e. the basic arithmetic unit and the advanced arithmetic unit. The basic arithmetic unit consists of two types of operations corresponding to the number of input operands, i.e. standard operations and non-standard operations. The standard operations are addition/subtraction and multiplication operations and the non-standard operations are product-of-sum and sum-of-product operations. The advanced arithmetic unit is frequently employed in scientific and engineering applications as elementary functions such as sine, cosine, hyperbolic sine, hyperbolic cosine, etc. The two classes of arithmetic units can be derived in hardware-based algorithmic form which is relatively easy for VLSI implementation and for analysis.
The binary-tree and partial linear methods are introduced to the leading-one-detection (LOD) and the integer multiplier in order to improve the performance of the floatingpoint standard and non-standard operators. The investigation and synthesis results that are based on the pipeline architecture show that both the proposed floating-point standard and nonstandard hardware-based algorithms can be simplified for VLSI implementation. Meanwhile, with the proposed LOD and the proposed integer multiplier, the floating-point standard and non-standard operators provide both high performance and time efficiency.
The advanced arithmetic functions are performed by the CORDIC algorithm, where the challenges of the CORDIC algorithm are to reduce computational latency and to improve computational accuracy. Therefore, two CORDIC methods, namely the doublerotation and triple-rotation, are proposed. Their performance, efficiency, and computational accuracy are measured, analysed, and compared with conventional CORDIC results using the Matlab/Simulink tools. The proposed CORDIC methods provide better performance, time efficiency, and computational accuracy than the conventional method, while at the same provided error constraints with few iterations. Similarly, with the same number of iterations, the proposed CORDIC methods present better computational accuracy than the conventional method. The unified micro-rotations of the proposed CORDIC methods are established and analysed in order to study the performance and efficiency based on several pipeline stages.
A high precision CORDIC algorithm, based on a unified micro-rotation of the proposed CORDIC methods, is introduced where the double-rotation and triple-rotation are applied for the normal-accuracy and high-accuracy mode, respectively. The high precision CORDIC core based on fixed-point representation is designed, implemented, and analysed. The synchronization between the floating-point standard unit, non-standard unit and the fixed-point elementary functional unit is demonstrated by floating-point arithmetic accelerator architecture and also by floating-point streaming processor architecture. The Floating-to-Fixed and Fixed-to-Floating algorithms are introduced for data conversion from floating-point to fixed-point representation and from fixed-point to floatingpoint representation.
Finally, the beam phase and magnitude detector that is employed in the closed-loop control system for heavy ion synchrotron application is used for verification of the proposed CORDIC methods. In the heavy ion synchrotron application, acceleration processes lead to beam signals with decreasing time periods for the pulses. Different modes of oscillation are possible. However, the current system deals with the simplest mode of oscillation, which is almost permanently presented, if no countermeasures are taken. The beam phase control system introduced here is dedicated to cases where all bunches are oscillating in phase. Therefore, the beam phase and magnitude detector is required to observe the beam oscillation for the closed-loop control system. The design of the digital phase and magnitude detector is modelled and simulated by VHDL on Model-Sim. The simulation results based on the two patterns, ”Gap voltage” and ”Beam position” generated and captured from the mathematic model and the actual ion synchrotron system, SIS18 at GSI Helmholtzzentrum Schwerionenforschung, are compared with the Matlab/Simulinks ideal results in order to verify the proposed CORDICs computation.
|Place of Publication:||Darmstadt, Germany|
|Classification DDC:||600 Technik, Medizin, angewandte Wissenschaften > 620 Ingenieurwissenschaften|
|Divisions:||Fachbereich Elektrotechnik und Informationstechnik|
|Date Deposited:||14 Nov 2012 08:24|
|Last Modified:||07 Dec 2012 12:05|
|License:||Simple publication rights for ULB|
|Referees:||Manfred, Prof. Glesner and Michael, Prof. Hübner and Andreas, Prof. Binder and Harald, Prof Klingbeil and Hans, Prof Eveking|
|Refereed:||17 August 2012|
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